Co-sponsored by: IEEE CAS Society, IEEE Signal Processing Society Chapter (Santa Clara Valley)
IEEE Circuits and Systems Society-Silicon Valley (CAS-SV) Artificial Intelligent For Industry Forum
Topic: Algorithm-architecture co-design for energy-efficient deep learning, including algorithm optimization (e.g., novel numerical representation, network pruning/compression) and accelerator architectures (e.g., programmable SoC).
(1) Dr. Pradeep Dubey from Parallel Computing Lab, Intel Labs, Intel Corporation (IEEE Fellow and Intel Fellow)
(2) Prof. Vivienne Sze from MIT, Associate Professor of Electrical Engineering and Computer Science, Electrical Engineering and Computer Science, (http://www.rle.mit.edu/people/directory/vivienne-sze/)
(3) Prof. Yung-Hsiang Lu from Purdue University, Professor in the School of Electrical and Computer Engineering (ACM distinguished speaker) (https://engineering.purdue.edu/ECE/People/ptProfile?resource_id=3355&group_id=2571)
(4) Dr. Mark Sandler, Google
Title: MobileNet: designing efficient architectures for mobile classification, detection and segmentation.
Abstract: In this talk we present lessons and insights that led us to design of MobileNet V1 and V2, discuss
common optimization techniques, such as quantization, and common pitfalls when designing
efficient architectures as well show our insights can guide automated architecture search.
Bio: Mark Sandler is a research scientist at Google, working among other things,
on next generation high performance neural networks for mobile vision.
IEEE Circuits and Systems Society and Intel Corporation
Co-Host: IEEE Circuits and Systems Society Santa Clara Valley Chapter, IEEE Signal Processing Society Santa Clara Valley Chapter, and IEEE Computer Society Technical Committee on Multimedia Computing
Speaker(s): Dr. Pradeep Dubey, Prof. Vivienne Sze
Bldg: SC12 auditorium
Intel Santa Clara
3600 Juliette Ln
Santa Clara, California