FPGA Heterogeneous Packaging Applications: Trends and Challenges

When:
November 14, 2018 @ 11:30 am – 1:00 pm America/Los Angeles Timezone
2018-11-14T11:30:00-08:00
2018-11-14T13:00:00-08:00
Where:
City: Santa Clara
Contact:
anmalik@ieee.org

Deep learning and artificial intelligence are at the heart of today’s technological innovations. Driven by advanced applications in HPC (High Performance Computing), Networking, Cloud Services and Automotive, demand for high bandwidth, lower latency and lower system power solutions have gained a lot of interest and momentum. As HPC designs move to several TB/sec and Telecom pushes to 400G/800G systems, bottlenecks in lower-latency memory bandwidth require HBM (High Bandwidth DRAM Memory) integration.
Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out InFO or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in a package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solutions are also becoming an active area of focus as the power levels are expected to push beyond 500W.
In this presentation we will examine FPGA Heterogeneous Packaging evolution working together with TSMC, industry trends and challenges. Since a system-level perspective is very important, we will touch upon some of the mechanical and thermal challenges and trends, and interplay with the package.

Speaker(s): Suresh,

Location:
Bldg: Texas Instruments Building E Conference Center
2900 Semiconductor Dr.
Santa Clara, California
95054